1. Field of the Invention
The present invention relates to a semiconductor storage device and, more particularly, to a semiconductor storage device having a multiple burst interrupt feature for switching burst operations on a priority basis.
2. Background of the Invention
FIG. 11 shows the layout of the entire configuration of a conventional DDR (Double Data Rate) type SDRAM (Synchronous Dynamic Random Access Memory). Referring to FIG. 11, the SDRAM shown includes four banks, BNK0 through BNK3, utilizes a 16-bit data bus for input and output of data and has a memory capacity of 256 Mbits.
Each bank BNKi (i=0 to 3) has 8K word lines (not shown), 8K pairs of bit lines (not shown) and 8K sense amplifiers (not shown), and has a memory capacity of 64 Mbits. Each bank BNKi inputs and outputs 16-bit data.
Each bank BNKi is divided into 16 arrays. FIG. 11 representatively illustrates arrays ARY2 and ARY3 of the bank BNK0 and an array ARY1 of the bank BNK1. Each array has 512 word lines, 8K pairs of bit lines and 8K sense amplifiers, and has a memory capacity of 4 Mbits. Each array inputs and outputs 16-bit data.
The SDRAM has a burst interrupt feature for interrupting a burst operation to start another burst operation. The burst interrupt feature will be explained, referring to the timing chart shown in FIG. 12. A burst read operation is shown with a CAS (Column Address Strobe) latency set to 2 clock cycles and a burst length of 8 bts. Since this SDRAM is the DDR type, it is capable of substituting 8-bit burst data by another 8-bit burst data storing at an odd position of the burst data. Specifically, burst data after the 3rd bit, 5th bit or 7th bit can be replaced by another burst data.
First, a command RAS1 is issued. The command RAS1 means inputting a row address in response to a RAS (Row Address Strobe). In response to the row address input by the command RAS1, a bank BNK1 is activated, and an array ARY1 in the bank BNK1 is activated. In this case, by the time the array ARY1 in the bank BNK1 is activated, the bank BNK0 has already been activated and an array ARY2 in the bank BNK0 has been activated.
Subsequently, a command R1CAS1 is issued. The command R1CAS1 means inputting a column address in response to a CAS. A burst read operation starts following two clocks from the command R1CAS1. Specifically, in an array ARY1 in the activated bank BNK1, data is consecutively read, beginning with the column address input by the command R1CAS1.
Subsequently, when a command R2CAS1 is issued following two clock cycles from the command R1CAS1, another burst read operation begins following two clock cycles from the command R2CAS1. Specifically, in an array ARY2 in another bank BNK0, data is consecutively read, beginning with the column address input by the command R2CAS1.
At this time, the burst read operation started in response to the command R1CAS1 is interrupted by the burst read operation started in response to the command R2CAS1. Specifically, the burst read operation begun in response to the command R1CAS1 is interrupted after the data of a 4th bit is read, and the data of a 5th bit and after is replaced by the data read by the burst read operation begun in response to the command R2CAS1.
Next, when a command R2CAS2 is issued, following two clock cycles from the command R2CAS1, another burst read operation begins following two clock cycles from the command R2CAS2. Specifically, in array ARY2 in the same bank BNK0, data is consecutively read, beginning with another column address input by the command R2CAS2.
At this time, the burst read operation started in response to the command R2CAS1 is interrupted by the burst read operation started in response to the command R2CAS2. Specifically, the burst read operation begun in response to the command R2CAS1 is interrupted after the data of the 4th bit is read, and the data of the 5th bit and after is replaced by the 8-bit data read by the burst read operation begun in response to the command R2CAS2.
Thus, even when a burst read operation is interrupted, the conventional SDRAM is capable of seamlessly outputting data if a new address input by the interruption is either a column address in another bank already activated or another column address currently being activated in the same array in the same bank. If, however, the new address is a column address other than the above, then seamless output of data cannot be realized.
For example, if an address is changed from array ARY2 to another array ARY3 even in the same bank BNK0, the array ARY2 must be first pre-charged to be activated in response to the command PRC1, then array ARY3 must be activated in response to a command RAS3. In this case, an 8-bit burst read operation begins only after two clocks following a command R3CAS3. This causes a gap equivalent to 8 bts to be produced in burst data to be output, resulting in a lower data rate.
The burst read operation interrupt occurs when priority is assigned to a computer program other than the currently executing computer program. In this case, a new address input for the interrupt is seldom a column address in the same row address. Therefore, the burst interrupt feature provided in the conventional SDRAM can rarely be utilized effectively.
In the case of the SDRAM shown in FIG. 11, if one of the sixteen arrays is selected and one word line in the selected array is activated, then 8K sense amplifiers are activated. Since the SDRAM has sixteen inputs/outputs, the page length per input/output is 512 (=8K÷16) bits. In other words, there are only 512 addresses allowing seamless interrupt to be handled. Even if all four banks BNK0 to BNK3 are activated, there are only 2K (=512xc3x974) addresses permitting seamless interrupt to be accomplished. This number is extremely limited for the total number of addresses 16M (=256M÷16) per input/output. The probability of successful seamless interrupts depends on the address space ratio (2K/16M), and is only 0.012%. This means that 99.998% of burst operation interrupt requests cannot be seamlessly handled. In most cases, therefore, a gap occurs in burst data to be output, resulting in a lower data rate.
Japanese Unexamined Patent Application Publication No. 2000-195253 (U.S. Pat. No. 6,252,794) has disclosed an SDRAM adapted to shorten a gap between burst operations by activating only the quantity of sense amplifiers corresponding to a burst length. The application, however, does not at all refer to a burst operation interrupt.
In the above description, the problems with the burst interrupt feature have been explained, taking the burst read operation as an example. The same problems are observed, however, also with a burst write operation.
An object of the present invention is to provide a semiconductor storage device permitting seamless input/output of data even when an interrupt takes place during a burst operation.
Another object of the present invention is to provide a semiconductor storage device having a higher probability of a valid interrupt for switching, on a priority basis, to a second burst operation while processing a first burst operation.
A semiconductor storage device according to one aspect of the present invention has a plurality of arrays, a plurality of burst read circuits, and a burst interrupt circuit. The plurality of arrays are activated independently from each other. The plurality of burst read circuits are provided, corresponding to the plurality of arrays. Each of the burst read circuits successively reads a plurality of bits of data from its corresponding array. The burst interrupt circuit activates a first burst read circuit while a second burst read circuit is activated.
In the semiconductor storage device, the arrays are activated independently from one another. Hence, an interrupt can be accepted while a plurality of bits of data is being successively read from one activated array, and a plurality of bits of data can be successively read from another activated array. This arrangement permits seamless output of burst data.
Preferably, the semiconductor storage device further includes a plurality of burst write circuits. The plurality of burst write circuits is provided, corresponding to the plurality of arrays. Each of the burst write circuits successively writes a plurality of bits of data to its corresponding array.
In this case, an interrupt is asserted while a plurality of bits of data is being successively written to one activated array, and a plurality of bits of data can be successively written to another activated array. Thus, seamless output of burst data is realizable.
A semiconductor storage device according to another aspect of the present invention includes a plurality of segment arrays, a plurality of segment selector circuits, a plurality of unit array selector circuits, a plurality of burst read circuits and a burst interrupt circuit. Each of the segment arrays includes a plurality of unit arrays. The plurality of segment selector circuits are provided, corresponding to the plurality of segment arrays. Each of the segment selector circuits activates its corresponding segment array. The plurality of unit array selector circuits are provided, corresponding to the plurality of segment arrays. Each of the unit array selector circuits selectively activates the plurality of unit arrays included in its corresponding segment array. The plurality of burst read circuits are provided, corresponding to the plurality of segment arrays. Each of the burst read circuits successively reads a plurality of bits of data from the unit array activated by a unit array selector circuit among the plurality of unit arrays included in its corresponding segment array. While at least one burst read circuit among the plurality of burst read circuits is being activated, the burst interrupt circuit activates another burst read circuit.
In the semiconductor storage device, the segment arrays are activated independently from one another. Hence, an interrupt can be accepted while a plurality of bits of data is being successively read from a unit array in one activated segment array, and a plurality of bits of data can be successively read from another activated segment array. This arrangement permits seamless output of burst data.
Preferably, each of the burst read circuits further includes a first prefetch latch circuit. The first prefetch latch circuit is activated in response to a first read enable signal, and latches a plurality of bits of data read from a unit array activated by a unit array selector circuit. The burst interrupt circuit activates the first read enable signal for the first prefetch latch circuit corresponding to the segment array activated by a segment selector circuit.
Further, each of the burst read circuits preferably includes a second prefetch latch circuit. The second prefetch latch circuit is activated in response to a second read enable signal, and latches a plurality of bits of data read from another unit array activated by a unit array selector circuit. The burst interrupt circuit activates the second read enable signal for the second prefetch latch circuit corresponding to the segment array activated by a segment selector circuit.
In this case, the plurality of bits of data read from one activated unit array is latched by the first prefetch latch circuit, and the plurality of bits of data read from another activated unit array is latched by the second prefetch latch circuit. This arrangement allows a burst reading interrupt to be accepted between unit arrays in a single segment array.
Preferably, the semiconductor storage device further includes a plurality of burst write circuits. The plurality of burst write circuits is provided, corresponding to the plurality of segment arrays. Each of the burst write circuits successively writes a plurality of bits of data to its corresponding segment array.
In this case, an interrupt is inserted while a plurality of bits of data is being successively written to one activated unit array, and a plurality of bits of data can be successively written to another activated unit array. Thus, seamless output of burst data is realized.
Additionally, each of the burst write circuits preferably includes a first preload latch circuit. The first preload latch circuit is activated in response to a first write enable signal, and latches a plurality of bits of data to be written to a unit array activated by a unit array selector circuit. The burst interrupt circuit activates the first write enable signal for the first preload latch circuit corresponding to the segment array activated by a segment selector circuit.
Further, each of the burst write circuits preferably includes a masking device for partly masking the plurality of bits of data latched by the first preload latch circuit.
In this case, an interrupt is inserted during a first burst write to a unit array, and the data latched by the first preload latch circuit after the interrupt is the data to be written to another unit array, causing the data to be masked by the masking device so as not to be written to the first unit array.
Preferably, each of the burst write circuits further includes a second preload latch circuit. The second preload latch circuit is activated in response to a second write enable signal, and latches a plurality of bits of data to be written to another unit array activated by a unit array selector circuit. The burst interrupt circuit activates the second write enable signal for the second preload latch circuit corresponding to the segment array activated by a segment selector circuit.
In this case, the plurality of bits of data written to one activated unit array is latched by the first preload latch circuit, and the plurality of bits of data written to another activated unit array is latched by the second preload latch circuit. This arrangement allows a burst writing interrupt to be accepted between unit arrays in a single segment array.